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ST72325AR7B3 Datasheet(PDF) 33 Page - STMicroelectronics |
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ST72325AR7B3 Datasheet(HTML) 33 Page - STMicroelectronics |
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33 / 197 page  ST72325xx 33/197 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2.2 Monitoring a Voltage on the EVD pin This mode is selected by setting the AVDS bit in the SICSR register. The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This in- terrupt is generated on the rising and falling edges of the comparator output. This means it is generat- ed when either one of these two events occur: –VEVD rises up to VIT+(EVD) –VEVD falls down to VIT-(EVD) The EVD function is illustrated in Figure 19. For more details, refer to the Electrical Character- istics section. Figure 19. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1) VEVD VIT+(EVD) VIT-(EVD) AVDF 0 0 1 IF AVDIE = 1 Vhyst AVD INTERRUPT REQUEST INTERRUPT PROCESS INTERRUPT PROCESS |
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