PIC16F720-ESLASHML datasheet(156/244 Pages) MICROCHIP

156 / 244 page

PIC16F/LF720/721

DS41430A-page 156

 2010 Microchip Technology Inc.

17.2.7

CLOCK STRETCHING

During any SCL low phase, any device on the I2C bus

may hold the SCL line low and delay, or pause, the

transmission of data. This “stretching” of a transmission

allows devices to slow down communication on the

bus. The SCL line must be constantly sampled by the

master to ensure that all devices on the bus have

released SCL for more data.

Stretching usually occurs after an ACK bit of a

transmission, delaying the first bit of the next byte. The

SSP module hardware automatically stretches for two

conditions:

• After a 10-bit address byte is received (update

SSPADD register)

• Anytime the CKP bit of the SSPCON register is

cleared by hardware

The module will hold SCL low until the CKP bit is set.

This allows the user slave software to update SSPBUF

with data that may not be readily available. In 10-bit

addressing modes, the SSPADD register must be

updated after receiving the first and second address

bytes. The SSP module will hold the SCL line low until

the SSPADD has a byte written to it. The UA bit of the

SSPSTAT register will be set, along with SSPIF,

indicating an address update is needed.

17.2.8

FIRMWARE MASTER MODE

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits of

the SSPSTAT register are cleared from a Reset or

when the SSP module is disabled (SSPEN cleared).

The Stop (P) and Start (S) bits will toggle based on the

Start and Stop conditions. Control of the I2C bus may

be taken when the P bit is set or the bus is Idle and both

the S and P bits are clear.

In Firmware Master mode, the SCL and SDA lines are

manipulated by setting/clearing the corresponding TRIS

bit(s). The output level is always low, irrespective of the

value(s) in the corresponding PORT register bit(s).

When transmitting a ‘1’, the TRIS bit must be set (input)

and a ‘0’, the TRIS bit must be clear (output).

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt will occur if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Firmware Master mode of operation can be done with

either the Slave mode Idle (SSPM<3:0> = 1011), or

with either of the Slave modes in which interrupts are

enabled. When both master and slave functionality is

enabled, the software needs to differentiate the

source(s) of the interrupt.

Refer

Application

Note

AN554,

“Software

Implementation of I2C™ Bus Master” (DS00554) for more

information.

17.2.9

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allow the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I2C bus may be taken when the P bit of the

SSPSTAT register is set or when the bus is Idle, and

both the S and P bits are clear. When the bus is busy,

enabling the SSP Interrupt will generate the interrupt

when the Stop condition occurs.

In Multi-Master operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is expected and a low level

is present, the device needs to release the SDA and

SCL lines (set TRIS bits). There are two stages where

this arbitration of the bus can be lost. They are the

Address Transfer and Data Transfer stages.

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be

generated. If arbitration was lost during the data

transfer stage, the device will need to re-transfer the

data at a later time.

Refer to Application Note AN578, “Use of the SSP

Module

the

I2C™

Multi-Master

Environment”

(DS00578) for more information.

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