PIC16F720-ESLASHML datasheet(154/244 Pages) MICROCHIP

154 / 244 page

PIC16F/LF720/721

DS41430A-page 154

 2010 Microchip Technology Inc.

17.2.6

TRANSMISSION

When the R/W bit of the received address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set and the slave will respond to

the master by reading out data. After the address match,

an ACK pulse is generated by the slave hardware and

the SCL pin is held low (clock is automatically stretched)

until the slave is ready to respond. See Section 17.2.7

“Clock Stretching”. The data the slave will transmit

must be loaded into the SSPBUF register, which sets

the BF bit. The SCL line is released by setting the CKP

bit of the SSPCON register.

An SSP interrupt is generated for each transferred data

byte. The SSPIF flag bit of the PIR1 register initiates an

SSP interrupt, and must be cleared by software before

the next byte is transmitted. The BF bit of the SSPSTAT

received clock pulse. The SSPIF flag bit is set on the

falling edge of the ninth clock pulse.

Following the 8th falling clock edge, control of the SDA

line is released back to the master so that the master

can acknowledge or not acknowledge the response. If

the master sends a not acknowledge, the slave’s

transmission is complete and the slave must monitor for

the next Start condition. If the master acknowledges,

control of the bus is returned to the slave to transmit

another byte of data. Just as with the previous byte, the

clock is stretched by the slave, data must be loaded into

the SSPBUF and CKP must be set to release the clock

line (SCL).

FIGURE 17-12:

I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF

CKP

ACK

Transmitting Data

R/W

Receiving Address

567

Cleared in software

Set bit after writing to SSPBUF

Data in

sampled

SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written to

before the CKP bit can be set)

Dummy read of SSPBUF

to clear BF flag

SSPBUF is written in software

From SSP Interrupt

Service Routine

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