AD9992BBCZ datasheet(63/92 Pages) AD

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AD9992

Rev. C | Page 63 of 92

Variable Gain Amplifier

The VGA stage provides a gain range of approximately 6 dB to

42 dB, programmable with 10-bit resolution through the serial

digital interface. A gain of 6 dB is needed to match a 1 V input

signal with the ADC full-scale range of 2 V. When compared to

1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.

The VGA gain curve follows a linear-in-dB characteristic. The

exact VGA gain is calculated for any gain register value by

Gain (dB) = (0.0358 × Code) + 5.75

where Code is the range of 0 to 1023.

VGA GAIN REGISTER CODE

127

255

383

511

639

767

895

1023

Figure 73. VGA Gain Curve

ADC

The AD9992 uses a high performance ADC architecture

optimized for high speed and low power. Differential non-

linearity (DNL) performance is typically better than 0.5 LSB.

The ADC uses a 2 V input range. See Figure 5 and Figure 7 for

typical linearity and noise performance plots for the AD9992.

Optical Black Clamp

The optical black clamp loop is used to remove residual offsets in

the signal chain and to track low frequency variations in the CCD’s

black level. During the optical black (shielded) pixel interval on

each line, the ADC output is compared with a fixed black level

reference, selected by the user in the clamp level register. The value

can be programmed between 0 LSB and 255 LSB in 1023 steps.

The resulting error signal is filtered to reduce noise; the correction

value is applied to the ADC input through a DAC. Normally,

the optical black clamp loop is turned on once per horizontal

line, but this loop can be updated more slowly to suit a particular

application. If external digital clamping is used during post-

processing, the AD9992 optical black clamping can be disabled

using Bit D2 in the AFE Register Address 0x00. When the loop is

disabled, the clamp level register can still be used to provide

fixed offset adjustment.

If the CLPOB loop is disabled, higher VGA gain settings reduce

the dynamic range because the uncorrected offset in the signal

path is amplified.

The CLPOB pulse should be aligned with the CCD’s optical

black pixels. It is recommended that the CLPOB pulse duration

be at least 20 pixels wide. Shorter pulse widths can be used, but

the ability for the loop to track low frequency variations in the

black level will be reduced. See the Horizontal Clamping and

Blanking section for timing examples.

Digital Data Outputs

The AD9992 digital output data is latched using the rising edge

of the DOUTPHASE register value, as shown in Figure 72.

Output data timing is shown in Figure 20 and Figure 21. It is

also possible to leave the output latches transparent so that the data

outputs are valid immediately from the ADC. Programming the

AFE Register Address 0x01, Bit D1, to 1 sets the output latches to

transparent. The data outputs can also be disabled (three-stated) by

setting the AFE Register Address 0x01, Bit D0, to 1.

The DCLK output can be used for external latching of the data

outputs. By default, the DCLK output tracks the values of the

DOUTPHASE registers. By changing the DCLKMODE register,

the DCLK output can be held at a fixed phase, and DOUTPHASE

with respect to DOUT, using the DCLKINV register bit.

The switching of the data outputs can couple noise back into

the analog signal path. To minimize switching noise, it is

recommended that the DOUTPHASE registers be set to the same

edge as the SHP sampling location, or up to 15 edges after the SHP

sampling location. Other settings can produce good results, but

experimentation is necessary. It is recommended that the

DOUTPHASE location not occur between the SHD sampling

location and 15 edges after the SHD location. For example, if

SHDLOC = 0, DOUTPHASE should be set to an edge location

of 16 or greater. If adjustable phase is not required for the data

outputs, the output latch can be left transparent by using

Address 0x01, Bit D1.

The data output coding is normally straight binary, but the coding

can be changed to gray coding by setting the AFE Register

Address 0x01, Bit D2, to 1.

AD9992BBCZ Datasheet(PDF) 63 Page - Analog Devices

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