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MPC5634MF0MMGA8 Datasheet(PDF) 90 Page - Freescale Semiconductor, Inc |
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MPC5634MF0MMGA8 Datasheet(HTML) 90 Page - Freescale Semiconductor, Inc |
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90 / 118 page  MPC5634M Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Electrical characteristics Freescale Semiconductor 90 3.16 AC timing 3.16.1 IEEE 1149.1 interface timing Table 33. JTAG pin AC electrical characteristics1 1 JTAG timing specified at V DD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V with multi-voltage pads programmed to Low-Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 34 for functional specifications. # Symbol C Characteristic Min. Value Max. Value Unit 1tJCYC CC D TCK Cycle Time 100 — ns 2tJDC CC D TCK Clock Pulse Width 40 60 ns 3tTCKRISE CC D TCK Rise and Fall Times (40% – 70%) — 3 ns 4tTMSS, tTDIS CC D TMS, TDI Data Setup Time 5 — ns 5tTMSH, tTDIH CC D TMS, TDI Data Hold Time 25 — ns 6tTDOV CC D TCK Low to TDO Data Valid —23 ns 7tTDOI CC D TCK Low to TDO Data Invalid 0 — ns 8tTDOHZ CC D TCK Low to TDO High Impedance — 20 ns 9tJCMPPW CC D JCOMP Assertion Time 100 — ns 10 tJCMPS CC D JCOMP Setup Time to TCK Low 40 — ns 11 tBSDV CC D TCK Falling Edge to Output Valid — 50 ns 12 tBSDVZ CC D TCK Falling Edge to Output Valid out of High Impedance —50 ns 13 tBSDHZ CC D TCK Falling Edge to Output High Impedance — 50 ns 14 tBSDST CC D Boundary Scan Input Valid to TCK Rising Edge 50 — ns 15 tBSDHT CC D TCK Rising Edge to Boundary Scan Input Invalid 50 — ns |
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