9

†† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25

°C and are for design aid only: not guaranteed and not subject to production testing.

*

Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high

impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i

.

AC Electrical Characteristics † - Clock Timing (Figures 12 and 13)

Characteristics

Sym

Min Typ ‡

Max

Units

Test Conditions

1

Clock Period*

220

244

300

ns

2

Clock Width High

95

122

150

ns

3

Clock Width Low

110

122

150

ns

4

Clock Transition Time

20

ns

5

Frame Pulse Setup TIme

20

ns

6

Frame Pulse Hold Time

0.020

670

µs

7

Frame Pulse Width

244

ns

C4i

FOi

Bit

Cells

Channel 31

Bit 0

Channel 0

Bit 7

C4i

F0i

2.0V

0.8V

2.0V

0.8V

Figure 12 Frame Allignment

Figure 13 Clock Timing