5

Figure 6 - Connection Memory Low Bits

switch and a second IMP8980D for

communication with the line interface

circuits.

A larger digital switching system may be

designed by cascading a number of

IMP8980Ds. Figure 9 shows four

IMP8980Ds arranged in a non-blocking

configuration which can switch any

channel on any of the ST-BUS inputs to

any channel on the ST-BUS outputs.

Application Circuit with 6802

Processor

Figure 10 shows an example of a

complete circuit which may be used to

evaluate the chip.

For convenience, a 4MHz crystal

oscillator has been used rather than a

4.096MHz clock, as both are within the

limits of the chip’s specifications. The RC

delay used with the 393 counters ensures a

sufficient hold time for the FP signal, but

the values used may have to be changed if

faster 393 counters become available.The

chip is shown as memory mapped into the

MEK6802D3 system. Chip addresses

00-3F correspond to processor addresses

2000-203F. Delay through the address

decoder requires the VMA signal to be

used twice to remove glitches. The

MEK6802D3 board uses a 10K

Ω pullup

on the MR pin, which would have to be

incorporated into the circuit if the board

was replaced by a processor.

76

54

32

10

Channel

Address

Bits

Stream

Address

Bits

BIT

NAME

DESCRIPTION

7-5*

Stream *

The number expressed in binary notation on these 3 bits is

Address

the number of the ST-BUS stream for the source of the connection.

Bits

Bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5

is 0, then the source of the connection is a channel on STi4.

4-0*

Channel

The number expressed in binary notation on these 5 bits is

Address

the number of the channel which is the source of the connection

Bits*

(The ST-BUS stream where the channel lies is defined by bits 7,

6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is

0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the

connection is channel 19.

* If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1,

then the entire 8 bits are output on the channel and stream associated with this location.

Otherwise, the bits are used as indicated to define the source of the connection which is

output on the channel and stream associated with this location.