CS5378 datasheet(37/88 Pages) CIRRUS

No. de pieza	CS5378

Descripción Electrónicos	Low-power Single-channel Decimation Filter

PDF	88 Pages

Scroll/Zoom	100%

Fabricante Electrónico	CIRRUS [Cirrus Logic]

Página de inicio	http://www.cirrus.com

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37 / 88 page

CS5378

DS639F2

10.4 Modulator Data Input

The MDATA input expects 1-bit

∆Σ data at a

512 kHz or 256 kHz rate. The input rate is selected

by a bit in the CONFIG register (0x00). By default,

MDATA is expected at 512 kHz.

The MDATA input one’s density is designed for

full scale positive at 86% and full scale negative at

14%, with absolute maximum over-range capabili-

ty to 93% and 7%. These raw

∆Σ inputs are deci-

mated and filtered by the digital filter to create 24-

bit samples at the output rate.

10.5 Modulator Flag Input

A high MFLAG input signal indicates the

∆Σ mod-

ulator has become unstable due to an analog over-

range input signal. Once the over-range signal is

reduced, the modulator recovers stability and the

MFLAG signal is cleared.

The MFLAG input is mapped to a status bit in the

serial data output stream, and is associated with

each sample when written. See “Serial Data Inter-

face” on page 58 for more information on the

MFLAG error bit in the serial data status byte.

CS5378 Datasheet(PDF) 37 Page - Cirrus Logic