STE100 datasheet(37/66 Pages) STMICROELECTRONICS

No. de pieza	STE100

Descripción Electrónicos	PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

PDF	66 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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STE10/100

5.4 Descriptors and Buffer Management

The STE10/100 provides receive and transmit descriptors for packet buffering and management.

5.4.1 Receive descriptor

Table 9. Receive Descriptor Table

Note: 1. Descriptors and receive buffers addresses must be longword aligned

ISOTX

Transmit Isolation. When 1, isolate from MII and tx+/-. This bit

must be 0 for normal operation

R/W

4~2

CMODE

Reports current transceiver operating mode.

000: in auto-negotiation

001: 10Base-T half duplex

010: 100Base-TX half duplex

011: reserved

100: reserved

101: 10Base-T full duplex

110: 100Base-TX full duplex

111: isolation, auto-negotiation disable

000

DISMLT

Disable MLT3.

0: the MLT3 encoder and decoder are enabled.

1: the MLT3 encoder and decoder are bypassed.

R/W

DISCRM

Disable Scramble.

0: the scrambler and de-scrambler is enabled.

1: the scrambler and de-scrambler are disabled.

R/W

RDES0

Own

Status

RDES1

---

Control

Buffer2 byte-count

Buffer1 byte-count

RDSE2

Buffer1 address (DW boundary)

RDSE3

Buffer2 address (DW boundary

Table 8. Transceiver registers Descriptions

Bit #

Name

Descriptions

Default Val

RW Type

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