STE100 datasheet(21/66 Pages) STMICROELECTRONICS

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STE10/100

31~17

---

reserved

NIE

Normal Interrupt Enable

1: enables all the normal interrupt bits (see bit 16 of CSR5)

R/W

AIE

Abnormal Interrupt Enable

1: enables all the abnormal interrupt bits (see bit 15 of CSR5)

R/W

---

reserved

FBEIE

Fatal Bus Error Interrupt Enable

1: this bit in conjunction with AIE (bit 15 of CSR7) will enable

the fatal bus error interrupt

R/W

---

Reserved

GPTIE

General Purpose Timer Interrupt Enable

1: this bit in conjunction with AIE (bit 15 of CSR7) will enable

the general purpose timer expired interrupt.

R/W

---

Reserved

RWTIE

Receive Watchdog Time-out Interrupt Enable

1: this bit in conjunction with AIE (bit 15 of CSR7) will enable

the receive watchdog time-out interrupt.

R/W

RSIE

Receive Stopped Interrupt Enable

1: this bit in conjunction with AIE (bit 15 of CSR7) will enable

the receive stopped interrupt.

R/W

RUIE

Receive Descriptor Unavailable Interrupt Enable

1: this bit in conjunction with AIE (bit 15 of CSR7) will enable

the receive descriptor unavailable interrupt.

R/W

RCIE

Receive Completed Interrupt Enable

1: this bit in conjunction with NIE (bit 16 of CSR7) will enable

the receive completed interrupt.

R/W

TUIE

Transmit Under-flow Interrupt Enable

1: this bit in conjunction with AIE (bit 15 of CSR7) will enable

the transmit under-flow interrupt.

R/W

---

Reserved

TJTTIE

Transmit Jabber Timer Time-out Interrupt Enable

1: this bit in conjunction with AIE (bit 15 of CSR7) will enable

the transmit jabber timer time-out interrupt.

R/W

TDUIE

Transmit Descriptor Unavailable Interrupt Enable

1: this bit in conjunction with NIE (bit 16 of CSR7) will enable

the transmit descriptor unavailable interrupt.

R/W

TPSIE

Transmit Processor Stopped Interrupt Enable

1: this bit in conjunction with AIE (bit 15 of CSR7) will enable

the transmit processor stopped interrupt.

R/W

TCIE

Transmit Completed Interrupt Enable

1: this bit in conjunction with NIE (bit 16 of CSR7) will enable

the transmit completed interrupt.

R/W

CSR8(offset = 40h), LPC - Lost packet counter

Table 6. Control/Status register description

Bit #

Name

Descriptions

Default Val

RW Type

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