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STE10/100

RDU

Receive Descriptor Unavailable

1: when the next receive descriptor can not be obtained by the

STE10/100. The receive process is suspended in this

situation. To restart the receive process, the ownership bit of

the next receive descriptor should be set to STE10/100 and a

receive poll demand command should be issued (if the receive

poll demand is not issued, the receive process will resume

when a new recognized frame is received).

RO/LH*

RCI

Receive Completed Interrupt

1: when a frame reception is completed.

RO/LH*

TUF

Transmit Under-Flow

1: when an under-flow condition occurs in the transmit FIFO

during transmitting. The transmit process will enter the

suspended state and report the under-flow errror on bit 1 of

TDES0.

RO/LH*

---

Reserved

TJT

Transmit Jabber Timer Time-out

1: when the transmit jabber timer expires. The transmit

processor will enter the stop state and TO (bit 14 of TDES0,

transmit jabber time-out flag) will be asserted.

RO/LH*

TDU

Transmit Descriptor Unavailable

1: when the next transmit descriptor can not be obtained by

the STE10/100. The transmission process is suspended in this

situation. To restart the transmission process, the ownership

bit of the next transmit descriptor should be set to STE10/100

and, if the transmit automatic polling is not enabled, a transmit

poll demand command should then be issued.

RO/LH*

TPS

Transmit Process Stopped.

1: while transmit state = stop

RO/LH*

TCI

Transmit Completed Interrupt.

1: set when a frame transmission completes with IC (bit 31 of

TDES1) asserted in the first transmit descriptor of the frame.

RO/LH*

LH = High Latching and cleared by writing 1.

CSR6(offset = 30h), NAR - Network access register

31~22

---

reserved

Store and forward for transmit

0: disable

1: enable, ignore the transmit threshold setting

R/W*

---

reserved

SQE

SQE Disable

0: enable SQE function for 10BASE-T operation. The STE10/

100 provides SQE test function for 10BASE-T half duplex

operation.

1: disable SQE function.

R/W*

18~16

-----

reserved

Table 6. Control/Status register description

Bit #

Name

Descriptions

Default Val

RW Type

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