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T89C51CC02CA-RATIM Datasheet(PDF) 69 Page - ATMEL Corporation |
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T89C51CC02CA-RATIM Datasheet(HTML) 69 Page - ATMEL Corporation |
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69 / 145 page  69 T89C51CC02 4126D–CAN–05/03 CAN Controller Mailbox and Registers Organization The pagination allows management of the 91 registers including 80(4 x 20) Bytes of mailbox via 32 SFRs. All actions on the message object window SFRs apply to the corresponding message object registers pointed by the message object number find in the Page message object register (CANPAGE) as illustrate in Figure 33. Figure 33. CAN Controller Memory Organization Ch.3 - ID Tag - 1 Ch.3 - ID Tag - 2 Ch.3 - ID Tag - 4 Ch.3 - ID Tag - 3 Ch.3 - ID Mask - 1 Ch.3 - ID Mask - 2 Ch.3 - ID Mask - 4 Ch.3 - ID Mask - 3 Ch.3 - Message Data - byte 0 General Control General Status bit Timing - 1 bit Timing - 2 bit Timing - 3 Enable Interrupt Enable Interrupt message object Page message object message object Status message object Control & DLC Message Data ID Tag - 1 ID Tag - 2 ID Tag - 4 ID Tag - 3 ID Mask - 1 ID Mask - 2 ID Mask - 4 ID Mask - 3 message object 0 - Status message object 0 - Control & DLC Ch.0 - ID Tag - 1 Ch.0 - ID Tag - 2 Ch.0 - ID Tag - 4 Ch.0 - ID Tag - 3 Ch.0 - Message Data - byte 0 message object 3 - Status message object 3 - Control & DLC Status Interrupt message object (message object number) (Data offset) SFRs On-chip CAN Controller Registers 4 Message Objects 8 Bytes TimStmp High TimStmp Low Ch.0 - ID Mask- 1 Ch.0 - ID Mask- 2 Ch.0 - ID Mask - 4 Ch.0 - ID Mask- 3 CANTimer High CANTimer Low TimTTC High TimTTC Low TEC counter REC counter Timer Control Enable message object message object Window SFRs Ch.0 TimStmp High Ch.0 TimStmp Low Ch.3 TimStmp High Ch.3 TimStmp Low General Interrupt |
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