ST72104G datasheet(37/135 Pages) STMICROELECTRONICS

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ST72104G, ST72215G, ST72216G, ST72254G

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MISCELLANEOUS REGISTERS (Cont’d)

10.3 MISCELLANEOUS REGISTER DESCRIPTION

MISCELLANEOUS REGISTER 1 (MISCR1)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = IS1[1:0]

ei1 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]

bits, is applied to the ei1 external interrupts. These

two bits can be written only when the I bit of the CC

ei1: Port B (C optional)

Bit 5 = MCO

Main clock out selection

This bit enables the MCO alternate function on the

PC2 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (fCPU on I/O

port)

Bit 4:3 = IS0[1:0]

ei0 sensitivity

The interrupt sensitivity, defined using the IS0[1:0]

bits, is applied to the ei0 external interrupts. These

two bits can be written only when the I bit of the CC

ei0: Port A (C optional)

Bit 2:1 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the SMS bit. These

two bits are set and cleared by software

Bit 0 = SMS

Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC /2

1: Slow mode. fCPU is given by CP1, CP0

See low power consumption mode and MCC

chapters for more details.

IS11

IS10

MCO

IS01

IS00

CP1

CP0

SMS

External Interrupt Sensitivity

IS11 IS10

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

External Interrupt Sensitivity

IS01 IS00

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

fCPU in SLOW mode

CP1

CP0

fOSC /4

fOSC /8

fOSC /16

fOSC /32

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