ST72104G datasheet(27/135 Pages) STMICROELECTRONICS

27 / 135 page

ST72104G, ST72215G, ST72216G, ST72254G

27/135

8 POWER SAVING MODES

8.1 INTRODUCTION

To give a large measure of flexibility to the applica-

tion in terms of power consumption, three main

power saving modes are implemented in the ST7

(see Figure 16).

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

main oscillator frequency divided by 2 (fCPU).

From Run mode, the different power saving

modes may be selected by setting the relevant

instruction whose action depends on the the oscil-

lator status.

Figure 16. Power Saving Mode Transitions

8.2 SLOW MODE

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (fCPU)to

the available supply voltage.

SLOW mode is controlled by three bits in the

MISCR1 register: the SMS bit which enables or

disables Slow mode and two CPx bits which select

the internal slow frequency (fCPU).

In this mode, the oscillator frequency can be divid-

ed by 4, 8, 16 or 32 instead of 2 in normal operat-

ing mode. The CPU and peripherals are clocked at

this lower frequency.

Note: SLOW-WAIT mode is activated when enter-

ring the WAIT mode while the device is already in

SLOW mode.

Figure 17. SLOW Mode Clock Transitions

POWER CONSUMPTION

WAIT

SLOW

RUN

HALT

High

Low

SLOW WAIT

SMS

CP1:0

fCPU

NEW SLOW

NORMAL RUN MODE

FREQU ENCY

REQUEST

fOSC/2

fOSC/4

fOSC/8

fOSC/2

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