ST72104G datasheet(84/135 Pages) STMICROELECTRONICS

84 / 135 page

ST72104G, ST72215G, ST72216G, ST72254G

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I2C BUS INTERFACE (Cont’d)

2C OWN ADDRESS REGISTER (OAR1)

Read / Write

Reset Value: 0000 0000 (00h)

7-bit Addressing Mode

Bit 7:1 = ADD7-ADD1

Interface address.

These bits define the I2C bus address of the inter-

face. They are not cleared when the interface is

disabled (PE=0).

Bit 0 = ADD0

Address direction bit.

This bit is don’t care, the interface acknowledges

either 0 or 1. It is not cleared when the interface is

disabled (PE=0).

Note: Address 01h is always ignored.

10-bit Addressing Mode

Bit 7:0 = ADD7-ADD0

Interface address.

These are the least significant bits of the I2C bus

address of the interface. They are not cleared

when the interface is disabled (PE=0).

2C OWN ADDRESS REGISTER (OAR2)

Read / Write

Reset Value: 0100 0000 (40h)

Bit 7:6 = FR1-FR0

Frequency bits.

These bits are set by software only when the inter-

face is disabled (PE=0). To configure the interface

to I2C specifed delays select the value corre-

sponding to the microcontroller frequency FCPU.

Bit 5:3 = Reserved

Bit 2:1 = ADD9-ADD8

Interface address.

These are the most significant bits of the I

2C bus

address of the interface (10-bit mode only). They

are not cleared when the interface is disabled

(PE=0).

Bit 0 = Reserved.

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

FR1

FR0

ADD9

ADD8

FCPU Range (MHz)

FR1

FR0

2.5 - 6

6 -10

10 - 14

14 - 24

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