LS1012A datasheet(6/39 Pages) NXP

6 / 39 page

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Table 1-1. Related documentation

Document

Description

QorIQ FRWY-LS1012A board Getting Started Guide

Explains the FRWY-LS1012A settings and physical

connections needed to boot the board.

FRWY-LS1012A Errata

Lists and describes all known errata for the FRWY-LS1012A.

It also describes the available workaround for each errata and

their detailed explanation, where necessary.

QorIQ LS1012A Family Reference Manual

Provides a detailed description of the LS1012A processor and

of some of its features, such as memory mapping, interfaces,

chip features, and clock information.

QorIQ LS1012A Data Sheet

Contains the LS1012A information on pin assignments,

electrical characteristics, package information, and ordering

information.

LS1012A Chip Errata

Lists the details of all known silicon errata for LS1012A.

QorIQ LS1012A Design Checklist, AN5192

This document provides recommendations for new designs

based on LS1012A.

This document can also be used to debug newly-designed

systems by highlighting those aspects of a design that merit

special attention during initial system start-up.

1.3 Acronyms and abbreviations

The following table lists the acronyms and abbreviations used in this document.

Table 1-2. Acronyms and abbreviations

Term

Description

DDR

Double Data Rate

UART

Universal asynchronous receiver/transmitter

DUT

Device Under Test

FET

Field-effect transistor

GPIO

General-purpose input/output

I2C

Inter-Integrated Circuit Multi-Master Serial Computer Bus

JTAG

Joint Test Action Group (IEEE 1149.1 standard)

LDO

Low-dropout

NGFF

Next Generation Form Factor

OTG

On-The-Go

PCIe

Peripheral Component Interconnect Express

PLL

Phased Lock Loop

Table continues on the next page...

Acronyms and abbreviations

Layerscape LS1012A Freeway (FRWY-LS1012A) Board Reference Manual, Rev. 0, 04/2018

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