M25P05-AVMP6TP datasheet(23/52 Pages) NUMONYX

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M25P05-A

Instructions

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Figure 10.

Read status register (RDSR) instruction sequence and data-out sequence

6.5

Write status register (WRSR)

The write status register (WRSR) instruction allows new values to be written to the status

been executed. After the write enable (WREN) instruction has been decoded and executed,

the device sets the write enable latch (WEL).

The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on Serial Data input (D).

The instruction sequence is shown in Figure 11.

The write status register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the

status register. b6, b5 and b4 are always read as 0.

Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.

If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven High, the self-timed write status register cycle (whose duration is tW) is initiated.

While the write status register cycle is in progress, the status register may still be read to

check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during

the self-timed write status register cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the write enable latch (WEL) is reset.

The write status register (WRSR) instruction allows the user to change the values of the

block protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only,

as defined in Table 2. The write status register (WRSR) instruction also allows the user to

set or reset the status register write disable (SRWD) bit in accordance with the Write Protect

(W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allow

the device to be put in the hardware protected mode (HPM). The write status register

(WRSR) instruction is not executed once the hardware protected mode (HPM) is entered.

The protection features of the device are summarized in Table 7.

When the status register write disable (SRWD) bit of the status register is 0 (its initial

delivery state), it is possible to write to the status register provided that the write enable latch

(WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the

whether Write Protect (W) is driven High or Low.

3456789 10 11 12 13 14 15

Instruction

AI02031E

6543210

Status register out

High Impedance

MSB

6543210

Status register out

MSB

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