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M25P05-AVMP6TP Datasheet(PDF) 20 Page - Numonyx B.V

No. de pieza M25P05-AVMP6TP
Descripción Electrónicos  512-Kbit, serial flash memory, 50 MHz SPI bus interface
PDF  52 Pages
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Fabricante Electrónico  NUMONYX [Numonyx B.V]
Página de inicio  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M25P05-AVMP6TP Datasheet(HTML) 20 Page - Numonyx B.V

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Instructions
M25P05-A
20/52
6.2
Write disable (WRDI)
The write disable (WRDI) instruction (Figure 8) resets the write enable latch (WEL) bit.
The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The write enable latch (WEL) bit is reset under the following conditions:
●
Power-up
●
Write disable (WRDI) instruction completion
●
Write status register (WRSR) instruction completion
●
Page program (PP) instruction completion
●
Sector erase (SE) instruction completion
●
Bulk erase (BE) instruction completion.
Figure 8.
Write disable (WRDI) instruction sequence
C
D
AI03750D
S
Q
2
1
34567
High Impedance
0
Instruction



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