IS25LE01G-RILA3 datasheet(169/186 Pages) ISSI

No. de pieza	IS25LE01G-RILA3

Descripción Electrónicos	SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	186 Pages

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Fabricante Electrónico	ISSI [Integrated Silicon Solution, Inc]

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169 / 186 page

IS25LE01G

IS25WE01G

Integrated Silicon Solution, Inc.- www.issi.com

169

Rev. A6

01/14/2025

8.66 PROGRAM NVDLR OPERATION (PNVDLR, 43h)

Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN)

command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded

successfully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.

The PNVDLR command (43h) is entered by shifting the instruction and data byte on SI.

CE# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the PNVDLR

command is not executed. As soon as CE# is driven to the logic high state, the self-timed PNVDLR operation is

initiated. While the PNVDLR operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the PNVDLR cycle, and is 0 when it is

completed. The PNVDLR operation can report a program error in the P_ERR bit of the Extended Read Register.

When the PNVDLR operation is completed, the Write Enable Latch (WEL) is set to 0 .

Figure 8.144 PNVDLR Sequence In SPI Mode

Instruction = 43h

CE #

SCK

Data In

Mode 3

Mode 0

High Impedence

Figure 8.145 PNVDLR Sequence In QPI Mode

43h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In

IS25LE01G-RILA3 Datasheet(PDF) 169 Page - Integrated Silicon Solution, Inc