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LSF0102 Datasheet(PDF) 19 Page - Texas Instruments |
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LSF0102 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 42 page ![]() 8.4 Layout 8.4.1 Layout Guidelines Because the LSF family is a switch-type level translator, the signal integrity is highly related with a pull-up resistor and PCB capacitance condition. • Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor. • Place LSF device close to the high voltage side. • Select the appropriate pull-up resistor that applies to translation levels and driving capability of the transmitter. 8.4.2 Layout Example LSF010x 1 GND 8 EN 2 Vref_A 7 Vref_B 3 A1 6 B1 4 A2 5 B2 Minimize Stub as possible Short Signal Trace as possible Figure 8-7. Short Trace Layout Device PCB TP1 SD Controller (1.8 V IO) TP2 LSF0108 SDIO level translator SDIO Connnector (3.3 V IO) LSF010x Figure 8-8. Device Placement www.ti.com LSF0102 SDLS972B – APRIL 2023 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LSF0102 |
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