Note:

* In reading data byte from HT1380/HT1381 register, the first data bit to be transmitted at the first falling edge

after the last bit of the command byte is written.

Rev. 1.10

8

July 18, 2008

S T A R T

E N D

I n p u t t h e w r i t e

p r o t e c t c o m m a n d

b y t e 8 E H

D i s a b l e t h e w r i t e

p r o t e c t b i t ( W P )

b y s e t t i n g t h e M S B

o f r e g i s t e r 7 t o z e r o

I n p u t t h e w r i t e

c o m m a n d b y t e 8 0 H

E n a b l e t h e o s c i l l a t o r

b y s e t t i n g t h e M S B o f

r e g i s t e r 0 t o z e r o

S T A R T

D i s a b l e t h e w r i t e p r o t e c t

b i t a n d e n a b l e t h e o s c i l l a t o r

R e a d o r w r i t e t h e

c o r r e s p o n d i n g r e g i s t e r d a t a

b y t e s t a r t i n g w i t h b i t 0

*

I n p u t t h e c o m m a n d

b y t e s t a r t i n g w i t h b i t 0

S T A R T

R e a d o r w r i t e a l l r e g i s t e r

d a t a b y t e ( 6 4 d a t a b i t s ) i n

t h e H T 1 3 8 1 s t a r t i n g w i t h

b i t 0 o f r e g i s t e r 0

*

I n p u t t h e b u r s t m o d e

c o m m a n d b y t e ( $ B E o r

$ B F ) s t a r t i n g w i t h b i t 0

E N D

D i s a b l e t h e w r i t e p r o t e c t

b i t a n d e n a b l e t h e o s c i l l a t o r

I f a n o t h e r r e g i s t e r

i s a c c e s s e d

E N D

Y e s

N o

S e t R E S T p i n

f r o m l o w t o h i g h

R e s e t R E S T p i n

f r o m h i g h t o l o w

S e t R E S T p i n

f r o m l o w t o h i g h

R e s e t R E S T p i n

f r o m h i g h t o l o w

R e s e t R E S T p i n

f r o m h i g h t o l o w

S e t R E S T p i n

f r o m l o w t o h i g h

S e t R E S T p i n

f r o m l o w t o h i g h

R e s e t R E S T p i n

f r o m h i g h t o l o w

· To disable the write protect

(WP=0) bit and enable the

oscillator (CH=0)

· Single byte data transfer

· Burst mode data transfer