The following diagram shows the single and burst mode transfer:

· Single Byte Transfer

· Burst Mode Transfer

The table illustrates the values suggested for capacities C1, C2

Part No.

Crystal Error

Capacity Value

HT1380/HT1381

±10ppm

5pF

10~20ppm

8pF

Operating Flowchart

To initiate any transfer of data, REST is taken high and an 8-bit command byte is first loaded into the control logic to pro-

vide the register address and command information. Following the command word, the clock/calendar data is serially

transferred to or from the corresponding register. The REST pin must be taken low again after the transfer operation is

completed. All data enter on the rising edge of SCLK and outputs on the falling edge of SCLK. In total, 16 clock pulses

are needed for a single byte mode and 72 for burst mode. Both input and output data starts with bit 0.

In using the HT1380/HT1381, set first the WP and CH to 0 and wait for about 3 seconds, the oscillator will generate the

clocks for internal use. Then, choose either single mode or burst mode to input the data. The read or write operating

flowcharts are shown on the next page.

Rev. 1.10

7

July 18, 2008

R / W

A 0

A 1 A 2

0

0

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

C o m m a n d B y t e

D a t a I / O

S C L K

I / O

R E S T

0

S C L K

I / O

0

1

D a t a B y t e 7

D a t a B y t e 0

R / W

0

1

2

3

4

5

6

7

1

1

1

1

1

0

7

0

7

R E S T

C o m m a n d B y t e