Rev. 1.10

6

July 18, 2008

Write Protect Register

This register is used to prevent a write operation to any

other register. Data can be written into the designated

register only if the Write Protect signal (WP) is set to

logic 0. The Write Protect Register should be set first be-

fore restarting the system or before writing the new data

to the system, and it should set as logic 1 in the read cy-

cle. The Write Protect bit cannot be written to in the burst

mode.

Clock HALT Bit

D7 of the Seconds Register is defined as the Clock Halt

Flag (CH).

When this bit is set to logic 1, the clock oscillator is

stopped and the chip goes into a low-power standby

mode. When this bit is written to logic 0, the clock will

start.

12-hour/24-hour Mode

The D7 of the hour register is defined as the 12-hour or

24-hour mode select bit.

When this bit is in high level, the 12-hour mode is se-

lected otherwise it

¢s the 24-hour mode.

AM-PM Mode

These are two functions for the D5 of the hour register

determined by the value D7 of the same register.

One is used in AM/PM selection on the 12-hour mode.

When D5 is logic 1, it is PM, otherwise it

¢s AM. The other

is used to set the second 10-hour bit (20~23 hours) on

the 24-hour mode.

Reset and Serial Clock Control

The REST pin is used to allow access data to the shift

register like a toggle switch. When the REST pin is taken

high, the built-in control logic is turned on and the ad-

dress/command sequence can access the correspond-

ing shift register. The REST pin is also used to terminate

either single-byte or burst mode data format.

The input signal of SCLK is a sequence of a falling edge

followed by a rising edge and it is used to synchronize

the register data whether read or write. For data input,

the data must be read after the rising edge of SCLK. The

data on the I/O pin becomes output mode after the fall-

ing edge of the SCLK. All data transfer terminates if the

REST pin is low and the I/O pin goes to a high imped-

ance state. The data transfer is illustrated on the next

page.

Data Input and Data Out

In writing a data byte with HT1380/HT1381, the

read/write should first set as R/W=0 in the Command

Byte and follow with the corresponding data register on

the rising edge of the next eight SCLK cycles. Additional

SCLK cycles are ignored. Data inputs are entered start-

ing with bit 0.

In reading a data on the register of HT1380/HT1381,

R/W=1 should first be entered as input. The data bit out-

puts on the falling edge of the next eight SCLK cycles.

Note that the first data bit to be transmitted on the first

falling edge after the last bit of the read command byte is

written. Additional SCLK cycles re-transmits the data

bytes as long as REST remains at high level. Data out-

puts are read starting with bit 0.

Crystal Selection

A 32768Hz crystal can be directly connected to the

HT1380/HT1381 via pin 2 and pin 3 (X1, X2). In order to

obtain the correct frequency, two additional load capaci-

ties (C1, C2) are needed. The value of the capacity de-

pends on how accurate the crystal is. We suggest that

you can follow the table on the next page.

3 2 7 6 8 H z

X 1

C 1

C 2

X 2