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MPC866 Datasheet(PDF) 44 Page - Freescale Semiconductor, Inc

No. de pieza MPC866
Descripción Electrónicos  Hardware Specifications
PDF  96 Pages
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MPC866 Datasheet(HTML) 44 Page - Freescale Semiconductor, Inc

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MPC866/MPC859 Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Bus Signal Timing
Table 14 shows the reset timing for the MPC866/859.
Table 14. Reset Timing
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
R69
CLKOUT to HRESET high impedance
(MAX = 0.00 x B1 + 20.00)
20.00 —
20.00 —
20.00 —
20.00 ns
R70
CLKOUT to SRESET high impedance
(MAX = 0.00 x B1 + 20.00)
20.00 —
20.00 —
20.00 —
20.00 ns
R71
RSTCONF pulse width (MIN = 17.00 x
B1)
515.20 —
425.00 —
340.00 —
257.60 —
ns
R72
——
——
——
R73
Configuration data to HRESET rising
edge setup time (MIN = 15.00 x B1 +
50.00)
504.50 —
425.00 —
350.00 —
277.30 —
ns
R74
Configuration data to RSTCONF rising
edge setup time (MIN = 0.00 x B1 +
350.00)
350.00 —
350.00 —
350.00 —
350.00 —
ns
R75
Configuration data hold time after
RSTCONF negation (MIN = 0.00 x B1 +
0.00)
0.00
0.00
0.00
0.00
ns
R76
Configuration data hold time after
HRESET negation (MIN = 0.00 x B1 +
0.00)
0.00
0.00
0.00
0.00
ns
R77
HRESET and RSTCONF asserted to
data out drive (MAX = 0.00 x B1 +
25.00)
25.00 —
25.00 —
25.00 —
25.00 ns
R78
RSTCONF negated to data out high
impedance (MAX = 0.00 x B1 + 25.00)
25.00 —
25.00 —
25.00 —
25.00 ns
R79
CLKOUT of last rising edge before chip
three-states HRESET to data out high
impedance (MAX = 0.00 x B1 + 25.00)
25.00 —
25.00 —
25.00 —
25.00 ns
R80
DSDI, DSCK setup (MIN = 3.00 x B1)
90.90
75.00
60.00
45.50
ns
R81
DSDI, DSCK hold time (MIN = 0.00 x B1
+ 0.00)
0.00
0.00
0.00
0.00
ns
R82
SRESET negated to CLKOUT rising
edge for DSDI and DSCK sample (MIN
= 8.00 x B1)
242.40 —
200.00 —
160.00 —
121.20 —
ns



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