MPC866 datasheet(38/96 Pages) FREESCALE

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MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

Bus Signal Timing

Figure 25 shows the interrupt detection timing for the external level-sensitive lines.

Figure 25. Interrupt Detection Timing for External Level Sensitive Lines

Figure 26 shows the interrupt detection timing for the external edge-sensitive lines.

Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines

Table 11 shows the PCMCIA timing for the MPC866/859.

Table 11. PCMCIA Timing

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

P44

A(0:31), REG valid to PCMCIA

Strobe asserted 1 (MIN = 0.75 x B1

– 2.00)

20.70

—

16.70

—

13.00

—

9.40

—

P45

A(0:31), REG valid to ALE

negation1 (MIN = 1.00 x B1 – 2.00)

28.30

—

23.00

—

18.00

—

13.20

—

P46

CLKOUT to REG valid (MAX = 0.25

x B1 + 8.00)

7.60

15.60

6.30

14.30

5.00

13.00

3.80

11.80

P47

CLKOUT to REG invalid (MIN =

0.25 x B1 + 1.00)

8.60

—

7.30

—

6.00

—

4.80

—

P48

CLKOUT to CE1, CE2 asserted

(MAX = 0.25 x B1 + 8.00)

7.60

15.60

6.30

14.30

5.00

13.00

3.80

11.80

P49

CLKOUT to CE1, CE2 negated

(MAX = 0.25 x B1 + 8.00)

7.60

15.60

6.30

14.30

5.00

13.00

3.80

11.80

CLKOUT

IRQx

I39

I40

CLKOUT

IRQx

I41

I42

I43

MPC866 Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc

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