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MPC866 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc |
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MPC866 Datasheet(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 96 page  MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 23 Bus Signal Timing B35 A(0:31), BADDR(28:30) to CS valid, as requested by control bit BST4 in the corresponding word in the UPM (MIN = 0.25 x B1 – 2.00) 5.60 — 4.30 — 3.00 — 1.80 — ns B35a A(0:31), BADDR(28:30), and D(0:31) to BS valid, as Requested by BST1 in the corresponding word in the UPM (MIN = 0.50 x B1 – 2.00) 13.20 — 10.50 — 8.00 — 5.60 — ns B35b A(0:31), BADDR(28:30), and D(0:31) to BS valid, as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 x B1 – 2.00) 20.70 — 16.70 — 13.00 — 9.40 — ns B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 x B1 – 2.00) 5.60 — 4.30 — 3.00 — 1.80 — ns B37 UPWAIT valid to CLKOUT falling edge 8 (MIN = 0.00 x B1 + 6.00) 6.00 — 6.00 — 6.00 — 6.00 — ns B38 CLKOUT falling edge to UPWAIT valid8 (MIN = 0.00 x B1 + 1.00) 1.00 — 1.00 — 1.00 — 1.00 — ns B39 AS valid to CLKOUT rising edge 9 (MIN = 0.00 x B1 + 7.00) 7.00 — 7.00 — 7.00 — 7.00 — ns B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge (MIN = 0.00 x B1 + 7.00) 7.00 — 7.00 — 7.00 — 7.00 — ns B41 TS valid to CLKOUT rising edge (setup time) (MIN = 0.00 x B1 + 7.00) 7.00 — 7.00 — 7.00 — 7.00 — ns B42 CLKOUT rising edge to TS valid (hold time) (MIN = 0.00 x B1 + 2.00) 2.00 — 2.00 — 2.00 — 2.00 — ns B43 AS negation to memory controller signals negation (MAX = TBD) — TBD — TBD — TBD — TBD ns 1 For part speeds above 50 MHz, use 9.80 ns for B11a. 2 The timing required for BR input is relevant when the MPC866/859 is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC866/859 is selected to work with the external bus arbiter. 3 For part speeds above 50 MHz, use 2 ns for B17. 4 The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of CLKOUT, in which the TA input signal is asserted. 5 For part speeds above 50 MHz, use 2 ns for B19. 6 The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats, where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) 7 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. Table 9. Bus Operation Timings (continued) Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit Min Max Min Max Min Max Min Max |
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