24-BIT x 4-AXES QUADRATURE COUNTER

FEATURES:

• Read/write registers for count and I/O modes.

Count modes include: non-quadrature (Up/Down), Quadrature

(x1, x2, x4), Free-run, Non-recycle, Modulo-n and Range limit

• Separate mode-control registers for each axis

• Interrupt output and interrupt mask register

• 40 MHz count frequency, 5V

20 MHz count frequency, 3V

• Sets of 24-bit counters, preset registers, comparators and

output latches and 8-bit status registers for each axis

• Digital filtering of the input quadrature clocks for

noise immumity.

• 3-state Octal I/O bus

• 3V to 5.5V operating voltage range

• LS7566R-TS (TSSOP) - See Figure 1 -

GENERAL DESCRIPTION:

The LS7566R consists of four identical modules of 24-bit pro-

grammable counters with direct interface to incremental encod-

ers. The modules can be configured to operate as quadrature-

clock counters or non-quadrature up/down counters. In both

quadrature and non-quadrature modes, the modules can be fur-

ther configured into free-running, non-recycle, modulo-n and

range-limit count modes. The mode configuration is made

through two 8-bit read/write addressable control registers, MDR0

and MDR1. Data can be ported to a 24-bit preset register PR, or-

ganized in directly addressable (write-only) byte0 [PR0], byte1

[PR1] and byte2 [PR2] segments. PR can be transferred to the

24-bit counter CNTR, either by instruction to MDR1 or by hard-

ware input control. A 24-bit digital comparator perpetually checks

for the equality of the CNTR and the PR and can be used to set

an output flag when the equality occurs. For reading the CNTR,

its instantaneous value can be transferred to a 24-bit output latch

OL, either by instruction to MDR1 or by hardware input control.

The OL in turn can be read in directly addressable (read-only)

byte0 [OL0], byte1 [OL1] and byte2 [OL2] segments. An address-

able (read-only) Octal status register STR, stores the count re-

lated status information such as CNTR overflow, underflow,

count direction, etc. Data communication for read/write is per-

formed through an Octal 3-state parallel I/O bus

.

REGISTER DESCRIPTION:

Following is a list of the hardware registers. There are four

sets of registers, with name prefixes x0 through x3 to refer

to axes x0 through x3.

The information included herein is believed to be

accurate and reliable. However, LSI Computer Systems,

Inc. assumes no responsibilities for inaccuracies, nor for

any infringements of patent rights of others which may

result from its use.

PIN ASSIGNMENT - Top View

December 2005

FIGURE 1

7566R-122205-1

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405

LS7566R

UL

®

A3800

1

48

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

RS2

RS1

RS0

CHS1

CHS0

NC

NC

RD/

CS/

WR/

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

NC

NC

PCK

GND

x0INDX/

x0A

x0FLGa

x0FLGb

x1FLGa

INT/

NC

GND

x1FLGb

x2FLGa

NC

x3FLGb

NC

x3B

x3A

x3INDX/

x2B

x2A

x2INDX/

x1B

x1A

x1INDX/

x0B

x2FLGb

x3FLGa