I/O PINS: The following is a description of the input/out pins.

RSO(Pin 3), RS1 (Pin 2), RS2 (Pin1).

Inputs. These three inputs select the hardware registers for read/write access according to Table 1.

TABLE 1

CS/

RS2

RS1

RS0

RD/

WR/

SELECTED REGISTER

OPERATION

1

x

x

x

x

x

none

none

x

x

x

x

0

0

none

none

x

x

x

x

1

1

none

none

0

0

0

0

0

1

[ISR:IMR]

READ (NOTE 2)

0

0

0

1

0

1

MDR0

READ

0

0

1

0

0

1

MDR1

READ

0

0

1

1

0

1

STR

READ

0

1

0

0

0

1

OL0

READ

0

1

0

1

0

1

OL1

READ

0

1

1

0

0

1

OL2

READ

0

1

1

1

0

1

none

none

0

0

0

0

1

0

IMR

WRITE

0

0

0

1

1

0

MDR0

WRITE

0

0

1

0

1

0

MDR1

WRITE

0

0

1

1

1

0

none

none

0

1

0

0

1

0

PR0

WRITE

0

1

0

1

1

0

PR1

WRITE

0

1

1

0

1

0

PR2

WRITE

0

1

1

1

1

0

CMR

WRITE

Note 1. x indicates don’t care case.

Note 2. DB0 through DB3 contain IMR B0 through B3; DB4 through DB7 contain ISR B0 through B3.

CHS0 (Pin 5), CHS1 (Pin 4)

Inputs. These two inputs select one of four axes for read/write access according to the following table. The

registers within the axis are selected according to Table 1.

TABLE 2

CHS1

CHS0

AXIS

0

0

x0

0

1

x1

1

0

x2

1

1

x3

RD/ (Pin 8) Input. A low on RD/ input accesses an ad-

dressed register for read and places the data on the

octal databus, DB<7:0>. The register selection is

made according to Table 1.

CS/ (Pin 9) Input. A low on the CS/ input enables the

chip for read or write operation. When the CS/ input is

high, read and write operations are disabled and the

databus, DB<7:0> is placed in a high impedance

state.

WR/ (Pin 10) Input. A low pulse on the WR/ input

writes the data on the databus, DB<7:0> into the ad-

dressed register according to Table 1. The write op-

eration is completed at the trailing edge of the WR/

pulse.

DB<7:0> (Pin 18 thru Pin 11) Input/Output.

The octal databus DB<7:0> is the input/output portal

for write and read data transfers between LS7566R

and the outside world. During a read operation, when

both CS/ and the RD/ inputs are low, DB<7:0> are

outputs. During a write operation, when both CS/ and

WR/ are low, DB<7:0> are inputs. When CS/ is high,

DB<7:0> are in high impedance state independent of

the states of RD/ and WR/.

PCK (Pin21) Input. A clock applied at PCK input is

used for validating the logic states of the A and B

quadrature clocks and the INDX/ input.

factor of 1 or 2 according to bit7 of MDR0. The re-

sultant clock is used to sample the logic levels of the

7566R-121605-5