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MPC8323ECVRADDC Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc

No. de pieza MPC8323ECVRADDC
Descripción Electrónicos  PowerQUICC??II Pro Integrated Communications Processor Family Hardware Specifications
PDF  80 Pages
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8323ECVRADDC Datasheet(HTML) 62 Page - Freescale Semiconductor, Inc

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
62
Freescale Semiconductor
Clocking
22 Clocking
Figure 43 shows the internal distribution of clocks within the MPC8323E.
Figure 43. MPC8323E Clock Subsystem
The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode, respectively.
22.1
Clocking in PCI Host Mode
When the MPC8323E is configured as a PCI host device (RCWH[PCIHOST] = 1), CLKIN is its primary
input clock. CLKIN feeds the PCI clock divider (
÷2) and the PCI_SYNC_OUT and PCI_CLK_OUT
Core PLL
System
LBC
LCLK[0:1]
core_clk
e300c2 core
csb_clk to Rest
CLKIN
csb_clk
MPC8323E
Local Bus
PCI_CLK_OUT[0:2]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the Device
lb_clk
PCI Clock
PCI_SYNC_IN
Memory
Device
/n
To Local Bus
Clock
Divider (
÷2)
MEMC1_MCK
MEMC1_MCK
2
DDR
ddr_clk
DDR
Memory
Device
PLL
QUICC
PLL
ce_clk to
To DDR
Memory
Controller
Clock
CFG_CLKIN_DIV
/2
Divider
Divider
2
3
Engine
QUICC Engine
Block



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