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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AT83SND2CMP3 Datasheet(PDF) 45 Page - ATMEL Corporation |
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AT83SND2CMP3 Datasheet(HTML) 45 Page - ATMEL Corporation |
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45 / 97 page  45 AT83SND2CMP3 7524B–MP3–05/06 Clock Controller The USB controller clock is generated by division of the PLL clock. The division factor is given by USBCD1:0 bits in USBCLK register. Figure 30 shows the USB controller clock generator and its calculation formula. The USB controller clock frequency must always be 48 MHz. Figure 30. USB Clock Generator and Symbol USBCD1:0 USBCLK 48 MHz USB Clock USBc lk PLLclk USBCD 1 + -------------------------------- = USB CLOCK USB Clock Symbol PLL CLOCK |
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