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AT83SND2CMP3 Datasheet(PDF) 32 Page - ATMEL Corporation |
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AT83SND2CMP3 Datasheet(HTML) 32 Page - ATMEL Corporation |
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32 / 97 page  32 AT83SND2CMP3 7524B–MP3–05/06 Register Table 29. AUXCON Register AUXCON (S:90h) – Auxiliary Control Register Reset Value = 1111 1111b 76 5 4 3 2 1 0 SDA SCL - AUDCDOUT AUDCDIN AUDCCLK AUDCCS KIN0 Bit Number Bit Mnemonic Description 7SDA TWI Serial Data SDA is the bidirectional Two Wire data line. 6SCL TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. 5 - Not used. 4 AUDCDOUT Audio Dac SPI Data Output. 3 AUDCDIN Audio Dac SPI Data Input 2 AUDCCLK Audio Dac SPI clock 1 AUDCCS Audio Dac Chip select Set to deselect DAC Clear to select DAC 0KIN0 Keyboard Input Interrupt. |
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