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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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USB97C100QFP Datasheet(PDF) 57 Page - SMSC Corporation |
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USB97C100QFP Datasheet(HTML) 57 Page - SMSC Corporation |
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57 / 64 page  SMSC DS – USB97C100 Page 57 Rev. 01/03/2001 Table 88 – 8051 IO WRITE Cycle NAME DESCRIPTION MIN MAX EQUIATION UNITS t1 SA[x] and AEN Valid to nIOW Asserted 106 4t-60 ns t2 nIOW Asserted to nIOW Deasserted 150 6t-100 ns t3 nIOW Deasserted to SA[x] Invalid 22 t-20 ns t4 SD[x] Valid to nIOW Deasserted 150 6t-100 ns t5 SD[x] Hold from nIOW Deasserted 22 t-20 ns t6 nIOW Deasserted to nIOW Asserted 25 ns t7 nIOW Deasserted to AEN Deasserted 22 t-20 ns t8 nIOW Deasserted to SD[x] tri-state 83 2t ns Note: Min and Max delays shown for 8051 clk of 24 MHz, to calculate typical timing delays for other clock frequencies use Oscillator Equations, where t=1/fCLK. FIGURE 11 – 8051 IO READ CYCLE Table 89 – 8051 IO Read Timing Parameters NAME DESCRIPTION MIN MAX EQUIATION UNITS t1 SA[x] and AEN Valid to nIOR Asserted 107 4t-60 ns t2 nIOR Asserted to nIOR Deasserted 150 6t-100 ns t3 nIOR Asserted to SA[x] Invalid 32 t-10 ns t4 nIOR Asserted to Data Valid 0 ns t5 Data Hold/Float from nIOR Deasserted 0 ns t6 nIOR Asserted after nIOR Deasserted 32 t-10 ns t7 nIOR Asserted after nIOW Deasserted 32 t-10 ns t8 nIOR Asserted to AEN Valid 10 ns t9 Data Valid to nIOR Deassereted 30 ns t10 nIOR Deasserted to SD[x] tri-state 32 t-10 ns Note: Min and Max delays shown for 8051 clk of 24 MHz, to calculate typical timing delays for other clock frequencies use Oscillator Equations, where t=1/fCLK. t3 t1 t2 t4 t5 DATA VALID AEN SA[x] nIOR SD[x] nIOW/nIOR t6 t7 t8 t9 t10 |
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