USB97C100QFP datasheet(26/64 Pages) SMSC

26 / 64 page

SMSC DS – USB97C100

Page 26

Rev. 01/03/2001

Table 31 - Wakeup Source 2 Register

WU_SRC_2

(0x7F2C - RESET=0x00)

WAKEUP SOURCE 2

BIT

NAME

R/W

DESCRIPTION

[7:4]

'0'

Reserved

IRQ3

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

IRQ2

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

IRQ1

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

IRQ0

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

Notes:

Any transition from high to low, or low to high on the associated input sets these bits. These bits are cleared

each time this register is read.

Since this register will report any status change, when devices are to be powered down while monitored, the

appropriate bits must be masked until the device is armed correctly.

Table 32 - Wakeup Mask 2 Register

WU_MSK_2

(0x7F2D - RESET=0x0F)

WAKEUP MASK 2

BIT

NAME

R/W

DESCRIPTION

[7 :4]

'0'

Reserved

IRQ3

R/W

External wakeup event enable.

0 = Enabled

1 = Masked

IRQ2

R/W

External wakeup event enable.

0 = Enabled

1 = Masked

IRQ1

R/W

External wakeup event enable.

0 = Enabled

1 = Masked

IRQ0

R/W

External wakeup event enable.

0 = Enabled

1 = Masked

Note: Interrupt events enabled by these bits are be routed to the PWR_MNG Bit 0 in the ISR_1 register.

USB97C100QFP Datasheet(PDF) 26 Page - SMSC Corporation

USB97C100QFP Datasheet(HTML) 26 Page - SMSC Corporation

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