USB97C100QFP datasheet(31/64 Pages) SMSC

No. de pieza	USB97C100QFP

Descripción Electrónicos	Multi-Endpoint USB Peripheral Controller

PDF	64 Pages

Scroll/Zoom	100%

Fabricante Electrónico	SMSC [SMSC Corporation]

Página de inicio	http://www.smsc.com

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31 / 64 page

SMSC DS – USB97C100

Page 31

Rev. 01/03/2001

Runtime Registers

The DMA controller has a block of 16 R/W registers which normally occupy I/O locations 0x00-0x0F on the ISA bus.

When they are located at 0x0000-0x000F on the ISA bus, the 8051 can access them by programming the IOBASE

Table 39 - 8237 Registers in ISA I/O Space

0x0000

Channel 0: Current Address H/L

0x0001

Channel 0: Byte Count H/L

0x0002

Channel 1: Current Address H/L

0x0003

Channel 1: Byte Count H/L

0x0004

Channel 2: Current Address H/L

0x0005

Channel 2: Byte Count H/L

0x0006

Channel 3: Current Address H/L

0x0007

Channel 3: Byte Count H/L

0x0008

Status/Command Register

0x0009

Write Request Register

0x000A

Write Single Mask Register

0x000B

Write Mode Register

0x000C

Clear Byte Ptr F/F - Read Temp

0x000D

Master Clear

0x000E

Clear Mask

0x000F

Write All Mask Bits

Note: To write to these registers, HLDA must be logic low.

USB97C100QFP Datasheet(PDF) 31 Page - SMSC Corporation