WM8772SEDSSLASHV datasheet(32/73 Pages) WOLFSON

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WM8772EDS – 28 LEAD SSOP

Production Data

PD Rev 4.2 October 2005

ADC AND DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the FMT[1:0] register bits:

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

1:0

FMT

[1:0]

Interface Format Select:

00 : Right justified mode

01: Left justified mode

10: I

2S mode

11: DSP mode A or B

In left justified, right justified or I

2S modes, the LRP register bit controls the polarity of LRC. If this bit

is set high, the expected polarity of LRC will be the opposite of that shown Figure 23, Figure 24 and

Figure 25. Note that if this feature is used as a means of swapping the left and right channels, a 1

sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select

between mode A and mode B.

BIT

LABEL

DEFAULT

DESCRIPTION

In left/right/I

2S Modes:

LRC Polarity (normal)

0 : Normal LRC polarity

1: Inverted LRC polarity

0000011

Interface Control

LRP

In DSP Mode:

0 : DSP mode A

1: DSP mode B

By default, LRC and DIN1/2/3 are sampled on the rising edge of BCLK and should ideally change on

the falling edge. By default, LRC and DOUT are sampled on the rising edge of BCLK and should

ideally change on the falling edge. Data sources that change LRC and DOUT on the rising edge of

BCLK can be supported by setting the BCP register bit. Data sources that change LRC and DIN1/2/3

on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1

inverts the polarity of BCLK to the inverse of that shown in Figure 23 to Figure 33.

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

BCP

BCLK Polarity (DSP Modes):

0: Normal BCLK polarity

1: Inverted BCLK polarity

The IWL[1:0] bits are used to control the input word length.

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

5:4

IWL

[1:0]

Input Word Length:

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note: 32-bit right justified mode is not supported.

In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the

DAC is programmed to receive 16 or 20 bit data, the WM8772EDS pads the unused LSBs with

zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.

Note: In 24 bit I

2S mode, any width of 24 bits or less is supported provided that LRC is high for a

minimum of 24 BCLKs and low for a minimum of 24 BCLKs.

A number of options are available to control how data from the Digital Audio Interface is applied to

the DAC channels.

WM8772SEDS/V Datasheet(PDF) 32 Page - Wolfson Microelectronics plc

WM8772SEDS/V Datasheet(HTML) 32 Page - Wolfson Microelectronics plc

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