WM8772SEDSSLASHV datasheet(24/73 Pages) WOLFSON

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WM8772EDS – 28 LEAD SSOP

Production Data

PD Rev 4.2 October 2005

AUDIO INTERFACE FORMATS

Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio

Interface. 5 popular interface formats are supported:

•

Left Justified mode

•

Right Justified mode

•

2S mode

•

DSP mode A

•

DSP mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the

exception of 32 bit right justified mode, which is not supported.

In left justified, right justified and I

2S modes, the digital audio interface receives DAC data on the

DIN1/2/3 inputs and outputs ADC data on DOUT. Audio Data for each stereo channel is time

multiplexed with LRC indicating whether the left or right channel is present. LRC is also used as a

timing reference to indicate the beginning or end of the data words.

In left justified, right justified and I

2S modes, the minimum number of BCLKs per LRC period is 2

times the selected word length. LRC must be high for a minimum of word length BCLKs and low for a

minimum of word length BCLKs. Any mark to space ratio on LRC is acceptable provided the above

requirements are met.

In DSP mode A or Mode B, all 6 DAC channels are time multiplexed onto DIN1. LRC is used as a

frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRC

period is 6 times the selected word length. Any mark to space ratio is acceptable on LRC provided

the rising edge is correctly positioned. The ADC data may also be output in DSP mode A or mode B,

with LRC used as a frame sync to identify the MSB of the first word. The minimum number of BCLKs

per LRC period is 2 times the selected word length if only the ADC is being operated.

LEFT JUSTIFIED MODE

In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8772EDS on the first rising edge of

BCLK following a LRC transition. The MSB of the ADC data is output on DOUT and changes on the

same falling edge of BCLK as LRC and may be sampled on the rising edge of BCLK. LRC is high

during the left samples and low during the right samples (Figure 23).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 23 Left Justified Mode Timing Diagram

WM8772SEDS/V Datasheet(PDF) 24 Page - Wolfson Microelectronics plc

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