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WM8772SEDS/V Datasheet(PDF) 46 Page - Wolfson Microelectronics plc |
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WM8772SEDS/V Datasheet(HTML) 46 Page - Wolfson Microelectronics plc |
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46 / 73 page ![]() WM8772EFT – 32 LEAD TQFP Production Data w PD Rev 4.2 October 2005 46 Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADCBCLK/DACBCLK cycle time tBCY 50 ns ADCBCLK/DACBCLK pulse width high tBCH 20 ns ADCBCLK/DACBCLK pulse width low tBCL 20 ns ADCLRC/DACLRC set-up time to ADCBCLK/DACBCLK rising edge tLRSU 10 ns ADCLRC/DACLRC hold time from ADCBCLK/DACBCLK rising edge tLRH 10 ns DIN1/2/3 set-up time to DACBCLK rising edge tDS 10 ns DIN1/2/3 hold time from DACBCLK rising edge tDH 10 ns DOUT propagation delay from ADCBCLK falling edge tDD 0 10 ns Table 15 Digital Audio Data Timing – Slave Mode MPU INTERFACE TIMING ML/I2S MC/IWL MD/DM t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 42 SPI Compatible Control Interface Input Timing |
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