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MCP3910 Datasheet(PDF) 49 Page - Microchip Technology |
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MCP3910 Datasheet(HTML) 49 Page - Microchip Technology |
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49 / 90 page ![]() 2012-2020 Microchip Technology Inc. DS20005116D-page 49 MCP3910 6.5.1 CONTINUOUS READ The STATUSCOM register contains the loop settings for the Internal Register Address Pointer (READ[1:0] bits and WRITE bit). For the Continuous Read modes, the address selection can take the four following values: No SDI data coming after the control byte are considered during a continuous read communication. The following figures represent a typical, continuous read communi- cation with the default settings (DR_LINK = 1, READ[1:0] = 10, WIDTH_DATA[1:0] = 01) for SPI Mode 0,0 (Figure 6-7) and SPI Mode 1,1 (Figure 6-8). In SPI Mode (1,1), the SDO pin stays in the last state (LSB of previous data) after a complete reading, which also allows seamless Continuous Read mode (see Figure 6-8). FIGURE 6-7: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 0,0). FIGURE 6-8: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 1,1). TABLE 6-1: ADDRESS SELECTION IN CONTINUOUS READ READ[1:0] Register Address Set Grouping for Continuous Read Communications 00 Static (no incrementation) 01 Groups 10 Types (default) 11 Full Register Map Note: For continuous reading of ADC data in SPI Mode 0,0 (see Figure 6-7), once the data have been completely read after a data ready, the SDO pin will take the MSB value of the previous data at the end of the reading (falling edge of the last SCK clock). If SCK stays Idle at logic low (by definition of Mode 0,0), the SDO pin will be updated at the falling edge of the next data ready pulse (synchronously with the DR pin falling edge with an output timing of tDODR) with the new MSB of the data corresponding to the data ready pulse. This mechanism allows the MCP3910 to continuously read ADC data outputs seamlessly, even in SPI Mode (0,0). Don’t care SCK SDI SDO CS Hi-Z 8x 0x01 24x DATA_CH0 Starts read sequence at address 00000 Complete READ sequence on ADC outputs channels 0 to 1 DATA_CH1 24x 24x DATA_CH0 DATA_CH1 24x Don’t care DR Stays at DATA_CH1<0> Complete READ sequence on new ADC outputs channels 0 to 1 High Z Don’t care SCK SDI SDO CS Hi-Z 8x 0x01 24x DATA_CH0 Starts read sequence at address 00000 DATA_CH1 24x 24x DATA_CH0 DATA_CH1 24x Don’t care DR DATA_CH0 <23> New data DATA_CH0 <23> Old data High Z |
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