Nexperia

74HC166; 74HCT166

8-bit parallel-in/serial out shift register

25 °C

-40 °C to +85 °C -40 °C to +125 °C

Symbol Parameter Conditions

Min Typ Max

Min

Max

Min

Max

Unit

CPD

power

dissipation

capacitance

per package;

VI = GND to VCC - 1.5 V

[3]

-

41

-

-

-

-

-

pF

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC 2 x fi + Σ (CL x VCC 2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

Σ (CL x VCC 2 x fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in V.

10.1. Waveforms and test circuit

aaa-008821

CP input

Q7 output

90 %

10 %

10 %

90 %

GND

VM

VI

VOH

VOL

VM

tW

tPHL

tPLH

tTLH

tTHL

1/fmax

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 8. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum

frequency

aaa-008822

Q7 output

VM

tPHL

VM

MR input

VM

tW

VI

GND

trec

VI

VOH

VOL

GND

CP input

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 9. Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time

74HC_HCT166

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 9 August 2021

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