Nexperia

74HC166; 74HCT166

8-bit parallel-in/serial out shift register

5. Pinning information

5.1. Pinning

74HC166

74HCT166

DS

VCC

D0

PE

D1

D7

D2

Q7

D3

D6

CE

D5

CP

D4

GND

MR

aaa-033054

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 5. Pin configuration for SOT109-1 (SO16)

74HC166

74HCT166

DS

VCC

D0

PE

D1

D7

D2

Q7

D3

D6

CE

D5

CP

D4

GND

MR

aaa-033055

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 6. Pin configuration for SOT403-1 (TSSOP16)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

DS

1

serial data input

D0 to D7

2, 3, 4, 5, 10, 11, 12, 14

parallel data inputs

CE

6

clock enable input (active LOW)

CP

7

clock input (LOW-to-HIGH edge-triggered)

GND

8

ground (0 V)

MR

9

asynchronous master reset (active LOW)

Q7

13

serial output from the last stage

PE

15

parallel enable input (active LOW)

VCC

16

positive supply voltage

74HC_HCT166

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 9 August 2021

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