AD9923ABBCZ datasheet(37/88 Pages) AD

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AD9923A

Rev. 0 | Page 37 of 88

Vertical Sensor Gate (Shift Gate) Patterns

In an interline CCD, the vertical sensor gates (VSG) are used to

transfer the pixel charges from the light sensitive image area

into the light shielded vertical registers. From the light shielded

vertical registers, the image is then read line-by-line using the

XV1 to XV13 vertical transfer pulses in conjunction with the

high speed horizontal clocks.

Table 19 summarizes the VSG pattern registers. The AD9923A

has eight VSG outputs, VSG1 to VSG8. Each output can be

assigned to one of eight programmed patterns by using the

SGPATSEL register. Each pattern is generated in a similar

manner as the V-pattern groups, with a programmable start

polarity (SGPOL), first toggle position (SGTOG1), and second

toggle position (SGTOG2). The active line where the VSG1 to

VSG8 pulses occur is programmable using the SGACTLINE1

and SGACTLINE2 registers. Additionally, any of the VSG1 to

VSG8 pulses can be individually disabled using the SGMASK

preprogrammed, and the appropriate pulses for each field can

be separately enabled. For maximum flexibility, the SGPATSEL,

SGMASK, and SGACTLINE registers are separately programmable

for each field. More detail is given in the Complete Field:

Combining V-Sequences section.

Additionally, there is the SGMASK_BYP register (Address 0x59)

that overrides SG masking in the field registers. The SGMASK_BYP

modifying the field register values. The SGMASK_BYP register

is SCK updated; therefore, the new SG-masking values update

immediately.

Table 19. VSG Pattern Registers1

Length

(Bits)

Range

Description

SGPOL

High/low

Sensor gate starting polarity for SG patterns 0 to 7.

SGTOG1

0 to 8191 pixel

location

First toggle position for SG patterns 0 to 7.

SGTOG2

0 to 8191 pixel

location

Second toggle position for SG patterns 0 to 7.

SGMASK_BYP

High/low for

each VSG

SGMASK Bypass. This register overrides the SGMASK values in each field register. One bit

for each output, where Bit[0] is for VSG1 output and Bit 7 is for VSG8 output.

0 = active.

1 = mask output.

SGMASK_BYP_EN

0 or 1

1: enables SGMASK bypass.

1 See field registers in Table 16.

PROGRAMMABLE SETTINGS FOR EACH PATTERN:

1START POLARITY OF PULSE.

2FIRST TOGGLE POSITION.

3SECOND TOGGLE POSITION.

4ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN).

VSG PATTERNS

Figure 50. Vertical Sensor Gate Pulse Placement

AD9923ABBCZ Datasheet(PDF) 37 Page - Analog Devices

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