DSP96002UMSLASHAD datasheet(21/111 Pages) NXP

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Signal/Connection Descriptions

OnCE Port

MOTOROLA

DSP96002/D, Rev. 2

1-17

DSO

Output

Output,

pulled

high

Debug Serial Output—

Data contained in one of the OnCE

controller registers is provided through the DSO output signal,

as specified by the last command received from the external

command controller. Data is always shifted out the OnCE

serial port MSB first. Data is clocked out of the OnCE serial

port on the rising edge of DSCK.

The DSO signal also provides acknowledge pulses to the

external command controller. When the chip enters the Debug

mode, the DSO signal will be pulsed low to indicate

(acknowledge) that the OnCE is waiting for commands. After

the OnCE receives a read command, the DSO signal will be

pulsed low to indicate that the requested data is available and

the OnCE serial port is ready to receive clocks in order to

deliver the data. After the OnCE receives a write command, the

DSO signal will be pulsed low to indicate that the OnCE serial

port is ready to receive the data to be written; after the data is

written, another acknowledge pulse will be provided.

Input

Debug Request—

The Debug Request input (DR) allows the

user to enter the Debug mode of operation from the external

command controller. When DR is asserted, it causes the DSP to

finish the current instruction being executed, save the

instruction pipeline information, enter the Debug mode, and

wait for commands to be entered from the DSI line. While in

Debug mode, the DR signal lets the user reset the OnCE

controller by asserting it and deasserting it after receiving

acknowledge. It may be necessary to reset the OnCE controller

in cases where synchronization between the OnCE controller

and external circuitry is lost. DR must be deasserted after the

OnCE responds with an acknowledge on the DSO signal and

before sending the first OnCE command. Asserting DR will

cause the chip to exit the Stop or Wait state. Having DR

asserted during the deassertion of RESET will cause the DSP to

enter Debug mode.

Note:

If the OnCE interface is not in use, attach an external pull-up

resistor to the DR input.

Table 1-8

On-Chip Emulation Port (OnCE) Signals (Continued)

Signal

Name

Signal

Type

State

during

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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