DSP96002UMSLASHAD datasheet(13/111 Pages) NXP

13 / 111 page

Signal/Connection Descriptions

Port A and Port B

MOTOROLA

DSP96002/D, Rev. 2

1-9

ATA

BTA

Input

Input,

ignored

during

reset

Transfer Acknowledge—

The TA input is a synchronous

“DTACK” function that can extend an external bus cycle

indefinitely. TA must be asserted and deasserted

synchronously to the input clock (CLK) for proper

operation. TA is sampled on the falling edge of the input

clock (CLK). Any number of wait states (0, 1, 2, …, infinity)

may be inserted by keeping TA deasserted. In a typical

operation, TA is first deasserted at the start of a bus cycle,

then is asserted to enable completion of the bus cycle, and

finally is deasserted before the next bus cycle.The current

bus cycle completes one clock period after TA is asserted

synchronously to CLK. The number of wait states is

determined by the TA input or by the Bus Control Register

(BCR), whichever is longer. The BCR can be used to set the

minimum number of wait states in external bus cycles. If

TA is tied low (asserted) and no wait states are specified in

the BCR, zero wait states will be inserted into external bus

cycles.

Note:

If the DSP96002 is the bus master and there is no external

bus activity or the DSP96002 is not the bus master, then

the TA input is ignored by the core.

AAE

BAE

Input

Input,

ignored

during

reset

Address Enable—

AE is an input that must be asserted and

deasserted synchronous to the input clock (CLK) for proper

operation. If the DSP is the bus master, AE is asserted to

enable the A0–A31 address output drivers. If AE is

deasserted, the address output drivers are tri-stated. If the

DSP is not a bus master, the address output drivers are tri-

stated regardless of whether AE is asserted or deasserted.

The function of AE is to allow implementation of

multiplexed bus systems. An example of such an

implementation is a multiplexed address1/address2 bus

used with dual port memories, such as dynamic VRAMs.

Note:

There must be at least one undriven CLK period between

enables for multiplexed buses to allow one bus to tri-

state before another bus is enabled. External control is

responsible for this timing. For non-multiplexed systems,

AE should be tied low.

Table 1-6

Port A and Port B (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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