LTC2421CMS datasheet(20/32 Pages) LINER

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LTC2421/LTC2422

24212f

Internal Serial Clock, Autostart Conversion

This timing mode is identical to the internal serial clock,

2-wire I/O described above with one additional feature.

Instead of grounding CS, an external timing capacitor is

tied to CS.

While the conversion is in progress, the CS pin is held

HIGH by an internal weak pull-up. Once the conversion is

complete, the device enters the low power sleep state and

an internal 25nA current source begins discharging the

capacitor tied to CS, see Figure 12. The time the converter

spends in the sleep state is determined by the value of the

external timing capacitor, see Figures 13 and 14. Once the

voltage at CS falls below an internal threshold (

≈1.4V), the

device automatically begins outputting data. The data out-

put cycle begins on the first rising edge of SCK and ends

on the 24th rising edge. Data is shifted out the SDO pin on

each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used to

shift the conversion result into external circuitry. After the

24th rising edge, CS is pulled HIGH and a new conversion

is immediately started. This is useful in applications re-

quiring periodic monitoring and ultralow power. Figure 15

shows the average supply current as a function of capaci-

tance on CS.

It should be noticed that the external capacitor discharge

current is kept very small in order to decrease the con-

verter power dissipation in the sleep state. In the autostart

mode, the analog voltage on the CS pin cannot be

observed without disturbing the converter operation

using a regular oscilloscope probe. When using this con-

figuration, it is important to minimize the external leakage

current at the CS pin by using a low leakage external ca-

pacitor and properly cleaning the PCB surface.

The internal serial clock mode is selected every time the

voltage on the CS pin crosses an internal threshold volt-

age. An internal weak pull-up at the SCK pin is active while

CS is discharging; therefore, the internal serial clock tim-

ing mode is automatically selected if SCK is floating. It is

important to ensure there are no external drivers pulling

SCK LOW while CS is discharging.

DIGITAL SIGNAL LEVELS

The LTC2421/LTC2422’s digital interface is easy to use.

Its digital inputs (FO, CS and SCK in External SCK mode of

operation) accept standard TTL/CMOS logic levels and the

internal hysteresis receivers can tolerate edge rates as

slow as 100

µs.However,someconsiderationsarerequired

Figure 11. Internal Serial Clock, Continuous Operation

APPLICATIO S I FOR ATIO

VCC

FSSET

ZSSET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

ZSSET + 0.1V TO VCC

0V TO FSSET – 100mV

CH0

= INTERNAL OSC/50Hz REJECTION

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

µF

110

2.7V TO 5.5V

LTC2422

VCC

10k

ANALOG INPUT RANGE

ZSSET – 0.12VREF TO

FSSET + 0.12VREF

(VREF = FSSET – ZSSET)

SDO

SCK

(INTERNAL)

LSB20

MSB

EXR

SIG

BIT 4

BIT 0

BIT 19

BIT 18

BIT 20

BIT 21

BIT 22

EOC

CH0/CH1

BIT 23

SLEEP

DATA OUTPUT

CONVERSION

24212 F11

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