FXPS7115D4S datasheet(33/74 Pages) NXP

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NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

Bit[1][2] Symbol

Description

INTREGA_ERR

The internal analog regulator voltage out-of-range error bit is set if the internal analog

regulator voltage falls outside expected limits.

0 — No error detected

1 — Internal analog regulator voltage out of range

INTREG_ERR

The internal digital regulator voltage out-of-range error bit is set if the internal digital regulator

voltage falls outside expected limits.

0 — No error detected

1 — Internal digital regulator voltage out of range

INTREGF_ERR

The internal OTP regulator voltage out-of-range error bit is set if the internal OTP regulator

voltage falls outside expected limits.

0 — No error detected

1 — Internal OTP regulator voltage out of range

CONT_ERR

The continuity monitor passes a low current through a connection around the perimeter of

the device and monitors the continuity of the connection. The error bit is set if a discontinuity

is detected in the connection.

0 — No error detected

1 — Error detected in the continuity of the edge seal monitor circuit

Table 40. DEVSTAT1 - device status register (address 02h) bit description...continued

[1]

During POR and soft reset ignore DEVSTAT1 error flags, refer to Section 7.5.5.

[2]

A common timer is used for all error bits in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV. This bit is cleared based

on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 7.7.4.

7.7.2.3 DEVSTAT2 - device status register (address 03h)

Bit

Symbol

F_OTP_

ERR

U_OTP_

ERR

U_RW_ERR

U_W_

ACTIVE

reserved

TEMP0_

ERR

reserved

Reset

reserved

Access

Table 41. DEVSTAT2 - device status register (address 03h) bit allocation

Bit

Symbol

Description

F_OTP_ERR

The NXP factory OTP array error bit is set if a fault is detected in the factory OTP array.

This error is cleared by a read of the DEVSTAT2 register through any communication

interface or on a data transmission that includes the error in the status field.

0 — No error detected

1 — Error detected in the NXP factory OTP array

U_OTP_ERR

The user OTP array error bit is set if a fault is detected in the user OTP array. This error is

cleared by a read of the DEVSTAT2 register through any communication interface or on a

data transmission that includes the error in the status field.

0 — No error detected

1 — Error detected in the user OTP array

Table 42. DEVSTAT2 - device status register (address 03h) bit description

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 9 August 2022

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FXPS7115D4S Datasheet(PDF) 33 Page - NXP Semiconductors

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