SPSB081 datasheet(23/135 Pages) STMICROELECTRONICS

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•

All outputs and V2 are turned off

•

All control registers are set to default values

•

Write operations to control registers are blocked until the fail-safe condition is cleared (see table below).

Only the following bits are not write-protected:

–

CR1 (0x01):

◦

TRIG

◦

CAN_ACT

–

CR2 (0x02):

◦

Timer settings (bits 8…13 and bits 16…21)

–

CR5 (0x05):

◦

OUT1_x (bits 0…2)

◦

OUT2_x (bits 4…6)

◦

OUT3_x (bits 8…10)

◦

OUT4_x (bits 12…14)

–

CR9 (0x09) to CR11 (0x0B)

◦

PWM frequency and duty cycles

–

Config register (0x3F)

◦

V2_0

◦

V2_1

•

LIN transmitter remains on

•

CAN FD transceiver remains on

•

Wake-up is enabled

•

Corresponding failure bits in status registers are set.

•

FS bit (bit 0 global status byte) is set

If the fail-safe mode was entered, it keeps active until the fail-safe condition is removed and the fail-safe was read

by SPI. Depending on the root cause of the fail-safe operation, the actions to exit fail-safe mode are as shown in

the following table.

Table 9. Temporary failures conditions

Failure source

Failure condition

Diagnosis

Exit from fail-safe mode

Microcontroller

(oscillator)

Watchdog

Early write failure or expired

window

FS (global status byte) =1

WDFAIL (SR1) =1

WDFAIL_CNT_x (SR1) = n+1

TRIG=1 during long open window

Read&Clear SR1

undervoltage

FS (global status byte) =1

V1UV (SR1)=1 (1)

V1FAIL (SR2)=1 (2)

V1 > VRTx

Read&Clear SR1

Temperature

Tj > TSD2

FS (global status byte) =1

TW (SR2) =1

TSD1 (SR1) =1

TSD2 (SR1) =1

Tj < TSD2

Read&Clear SR1

1. bit V1UV in SR1 is set for t > tuv1 (16 µs). Fail-Safe bit GSR/FS is set only after trd (NRESET low pulse).

2. If V1 < V1fail (for t > tv1fail). The fail-safe bit is located in the global status register.

3.7.2

Non recoverable failures –Forced in VBAT_standby mode

If the fail-safe condition persists and all attempts to return to normal system operation fail, the SPSB081 is forced

into VBAT_standby mode to prevent damage to the system. The VBAT_standby mode can be terminated by any

wake-up source. The root cause of the VBAT_standby is indicated in the SPI status registers.

In VBAT_standby mode, all control registers are set to power on default.

The VBAT_standby mode is entered in case of:

SPSB081

Fail safe mode

DS14048 - Rev 1

page 23/135

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