L99LD21 datasheet(33/73 Pages) STMICROELECTRONICS

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DS11130 Rev 5

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L99LD21

SPI functional description

5.4

Registers description

5.4.1

Control Register description

CR#1: Control Register 1

Address:

0x01h

Type:

R/W

14h

WD bit pos. 2

D7h

Bit7, WB1 = 1

Bit6, WB0 = 1

Bit position of the WD bit within the

corresponding configuration register = 23d =

010111b

20h

SPI CPHA Test

55h

Predefined by ST - SPI , it is used to verify that

the SCK Phase of the SPI master is set correctly

3Eh

GSB Options

00h

All bits of GSB are used

3Fh

Advanced

Operation Code

R00h

Access to this address provokes a SW reset (all

control registers are set to their default values; in

addition, all status registers are cleared too).

Data field should not be all ones, otherwise an SDI

stuck occurs

Table 13. ROM memory map (continued)

Address

Name

Access Content

Comments

9876

543210

DUTY1

DUTY2

Table 14. CR#1: Control Register 1

Bit

Default

Name

Description

23÷14

1000000000

DUTY1

10 bit PWM duty cycle selection for Buck1 (from 0 to hex 3FF) Default

50%

13÷4

1000000000

DUTY2

10 bit PWM duty cycle selection for Buck2 (from 0 to hex 3FF) Default

50%

Set by OTP

(DEF_HLEDCUR)

HLEDCUR1

[1]: High LED current configuration selected for Buck1 (Low RON, both

half power stages enabled)

[0]: Low LED current configuration selected for Buck1 (High RON, only

one half power stage enabled)

HLEDCUR2

[1]: High LED current configuration selected for Buck2 (Low RON, both

half power stages enabled)

[0]: Low LED current configuration selected for Buck2 (High RON, only

one half power stage enabled)

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