L6364 datasheet(42/60 Pages) STMICROELECTRONICS

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Surge pulse and reverse polarity protections

The PGND, CQ, DIO and VPLUS pins are fully protected by a surge protection, to withstand an asymmetric surge

between any pair of these pins according to IEC 60255-5, i.e. > 2 APK (up to 3 APK) for a half-time of 50 μs.

Note that the surge stimulus is applied between the pins, rather than in common mode. This subjects the device

under test to the current ratings shown in Figure 19.

Figure 19. Surge waveform

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

100

120

140

t (µs)

The surge protection provides a Zener like action with a protection threshold of VVSURGE(CLAMP), deliberately

chosen to be in excess of the normal operating voltages of the L6364.

Once the surge disturbance is complete, the line voltages recover to normal levels and the Zener protection

automatically ceases to conduct.

This protection style is preferred over an active snap-back protection which may continue to conduct when the

operating voltages return to their nominal conditions.

Further external surge protections are compatible with the internal protections where compliance to standards

exceeding the demands of IEC 60255-5 are required.

Reverse polarization protection is included in the L6364. When V3V3 is not supplied (VVPLUS ≤ VPGND) minimal

currents, IPLUSREV, flow between any pair of the pins, up to a maximum voltage difference between any pair of

pins of 35 V.

Note:

if the L6364 is rapidly switched from a correctly polarized condition to a reverse polarized condition, such that

the CV3V3 capacitor remains charged, then the Zener function of the CQ output causes a destructive current to

flow.

Sufficient time should be allowed (ms) during testing of the reverse polarization function to allow CV3V3 to

discharge.

L6364

Surge pulse and reverse polarity protections

DS13363 - Rev 4

page 42/60

L6364 Datasheet(PDF) 42 Page - STMicroelectronics