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STM32H750IB Datasheet(PDF) 51 Page - STMicroelectronics |
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STM32H750IB Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 337 page  DS12556 Rev 6 51/336 STM32H750VB STM32H750ZB STM32H750IB STM32H750XB Functional overview 52 The devices include the following features: • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time 3.43 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on data reception. 3.44 Debug infrastructure The devices offer a comprehensive set of debug and trace features to support software development and system integration. • Breakpoint debugging • Code execution tracing • Software instrumentation • JTAG debug port • Serial-wire debug port • Trigger input and output • Serial-wire trace port • Trace port • Arm® CoreSight™ debug and trace components The debug can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools. The trace port performs data capture for logging and analysis. |
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