STM32H750IB datasheet(50/337 Pages) STMICROELECTRONICS

50 / 337 page

Functional overview

STM32H750VB STM32H750ZB STM32H750IB STM32H750XB

50/336

DS12556 Rev 6

3.41

Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG

peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2

supports only full-speed operations. They both integrate the transceivers for full-speed

operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1

features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using

the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.

The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the

OTG 2.0 specification. They have software-configurable endpoint setting and supports

suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is

generated by a PLL connected to the HSE oscillator.

The main features are:

•

Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

9 bidirectional endpoints (including EP0)

•

16 host channels with periodic OUT support

•

Software configurable to OTG1.3 and OTG2.0 modes of operation

•

USB 2.0 LPM (Link Power Management) support

•

Battery Charging Specification Revision 1.2 support

•

Internal FS OTG PHY support

•

External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)

The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can

be clocked using the 60 MHz output.

•

Internal USB DMA

•

HNP/SNP/IP inside (no need for any external resistor)

•

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

3.42

Ethernet MAC interface with dedicated DMA controller (ETH)

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for

ethernet LAN communications through an industry-standard medium-independent interface

(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an

external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,

fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals

for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.

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